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pt4301 low power high sensitivity 315/434mhz ook/ask superheterodyne receiver tel: 886-66296288 ? fax: 886-29174598 ? http://www.princeton.com.tw ? 2f, 233-1, baociao road, sindian, taipei 23145, taiwan description the pt4301 is a very low power and highly sensitive single chip ook/ask super-heterodyne receiver for the 315mhz and 434mhz frequency bands that offers a high level of integration and requires only a few external components. the pt4301 consists of a low-noise amplifier (lna), an image-rejection mixer, an on-chip phase-locked loop (pll) with integrated voltage-controlled oscillator (vco) and loop filter, a 10.7mhz intermediate frequency (if) limiting amplifier stage with received-signal-s trength indicator (rssi), and analog baseband data recovery circuitry (data filter, peak detector, and dat a slicer). the pt4301 also implements a discrete one-st ep automatic gain control (agc) that reduces the lna gain by 20db when the rf input signal is greater than -47dbm. the pt4301 is available in a 24-pin ssop package. features ? low current consumption (5ma fully active mode at 315mhz) ? 2.4v to 5.5v supply voltage operation range ? optimized for 315mhz or 434mhz ism band ? on-chip image-rejection function ? high dynamic range with on-chip agc ? low power down mode current (<1 a) ? high sensitivity of - 114dbm (315mhz, 2kb/s am 99% square-wave modulation) ? 24-pin ssop package applications ? remote keyless entry (rke) systems ? remote control systems including garage door and gate openers ? alarm and security systems ? wireless sensors block diagram for:natertech
pt4301 v1.4 2 october 2010 application circuit xout 1 regif 2 lnain 3 vsslna 4 lnaout 5 regrf 6 mixin 7 vssmix 8 mixout 9 vssdig 10 regdig 11 agcdis 12 limin 13 liminb 14 dfo 15 dsn 16 opp 17 dffb 18 dsp 19 vdd5 20 data 21 pdout 22 ce 23 xin 24 ptc pt4301 x1 ce pwr vdd5 c1 c2 c3 c4 l1 c5 c6 c7 l2 r1 f1 c8 c10 c9 r2 c11 c12 r5 r4 c14 c15 c13 r3 u1 r6 c16 regdig l3 r7 bill of materials component value unit description 315mhz 434mhz r1, r4 10 10 ? power supply de-coupling resistors (option) r2 27k 27k ? data filter to data slicer interface resistor r3 8.2m 8.2m ? data slicer threshold adjustment (option) r5 220k 220k ? data filter to data slicer interface resistor r6 100k 100k ? agc disable r7 5.6k 5.6k ? regdis discharge resistor (option) l1 68n 39n h lna input matching, coil inductor l2 47n 27n h lna output matching l3 39n 27n h antenna esd protection, coil inductor (option) c1 n o t e 1 ,c7, c12 100n 100n f power supply de-coupling resistors c2 10p 10p f lna input matching c3 - - f lna input matching (option) c4 1.8p 1.2p f lna input matching c5 - - f lna output matching (option) c6 100p 100p f lna to mixer interface capacitor c8 1.5n 1.5n f if amplifier de-coupling capacitor c9 470n 470n f data slicer threshold charge capacitor c10 390p 390p f data filter capacitor c11 1.2n 1.2n f data filter capacitor c13 - - f peak mode charge capacitor (option) c14, c15 27p 27p f crystal oscilla tor frequency fine tune capacitors c16 100n 100n f agc high gain mode quick start capacitor f1 n o t e 2 10.7 10.7 mhz if filter x1 9.509 13.226 mhz reference crystal oscillator u1 pt4301 ic pt4301 ic - receiver chip notes: 1. c1 could be separated into three de-coupling capacitors and c onnect them against the three vdd pins as close as possible. 2. f1 is the 10.7mhz ceramic filter. the re commended part number is murata sfela10m7ha00-b0. for:natertech
pt4301 v1.4 3 october 2010 order information valid part number package type top code PT4301-X 24 pins, ssop, 150mil PT4301-X pin configuration pin description pin name i/o description pin no. xout o crystal oscillator output 1 regif p supply voltage for if portion 2 lnain i lna input 3 vsslna g ground for lna 4 lnaout o lna output 5 regrf p supply voltage for rf portion 6 mixin i mixer input 7 vssmix g ground for image-rejection mixer 8 mixout o mixer output 9 vssdig g ground for lo and digital portions 10 regdig p supply voltage for lo and digital portions 11 agcdis i agc control pin. pull high (connect to vdd5) to disable agc 12 limin i limiting amplifier input 13 liminb i limiter amplifier de-coupling input 14 dfo o data filter output 15 dsn i negative data slicer input 16 opp i non-inverting op-amp input for sallen-key data filter 17 dffb i/o data filter feedback node 18 dsp i positive data slicer input 19 vdd5 p 5v supply voltage 20 data o data output 21 pdout o peak detector output 22 ce i chip enable pin. pull high (connect to vdd5) to power on the chip 23 xin i crystal oscillator input 24 note: pin 13 and pin 14 are identical pins. us ers can choose either pin as the limiti ng amplifier input and treat the other pin as the de-coupling input. for:natertech
pt4301 v1.4 4 october 2010 function description the pt4301 cmos superheterodyne receiver achieves both low power consumpt ion and high sensitivity and functions as a complete receive chain from antenna input to di gital data output. depending upon t he component selection, data rates as high as 50kb/s may be achieved at both 315 and 434mhz frequency bands. low noise amplifier (lna) the lna is an on-chip cascade amplifier with a power gain of 16db and a noise figure of approximately 3db. the gain is determined by external matching networks in front of the lna and between the lna output and the mixer input. examples of the input matching net work and the input impedance of the pt 4301 for 315/434mhz bands are shown in figure 1. the component values given in the table following the application circ uit shown in page 2 are nominal values only. for a particular pcb layout, the user may be requir ed to make component adjustments in order to achieve highest sensitivity. frequency(mhz) lna input impedance (pin 3) normalized to 50 ? 315 2.45-j138.4 433.92 3.05-j194.85 figure 1. lna input matching ci rcuit and input impedance of pt4301 the lna output of pt4301 externally connects to the mixe r stage. for the interface bet ween the lna and mixer, the coupling capacitor should be as close to the pt4301 pins as possible, with the bias i nductor being further away. the value of the inductor may be changed to compensate for tr ace inductance. for obtaini ng better lna gain, it is recommended to add a capacitor in parallel with this inductor to implement a re sonant tank at the desired frequency as shown in figure 2. note that the lna might self-oscillate and degrade the receiver sensitivity if a large output inductor value is chosen. an alternative matching method is to replace the parallel capacitor with a 330 ? to 1k ? resistor, which would reduce the resonant tank q (quality factor) to avoid the self-oscillation. figure 2. lna output matching circuit the lna incorporates gain control circuitry. when the r ssi voltage exceeds a threshold reference value corresponding to an rf input level of approximately - 47dbm, the agc switches on the lna gain reduction resistor. the loading resistor reduces the lna gain by 20db, thereby reducing the rssi output by approximat ely 260mv. the threshold reference voltage which is compared with the rssi voltage to determi ne the gain state of the lna is also reduced. the lna resumes high-gain mode when the rssi voltage drops bel ow this lower threshold voltage corresponding to approximately -63dbm rf input. the agc incorporates an additional protection mechanism (delay timer of 2 20 t ref seconds) to prevent immediate resetting of the lna back to the high-gain stat e during reception of a ?space? for ook/ask modulation. for:natertech
pt4301 v1.4 5 october 2010 mixer a special feature of the pt4301 is its integrated double-balanced image-rejection mi xer, which eliminates the need for a costly front-end saw filter for many applications. the advantages of not usi ng a saw filter include simplified antenna matching, less board space, and lower bom cost. the mixer ce ll is a pair of double-balanced mixers that perform an iq down-conversion of the rf i nput to the 10.7mhz if with low-side injection (i.e. f lo = f rf ? f if ). the image-rejection circuit then combines these signals to achieve a typical 35db of image-rejection ratio. low-side injection is required since high-side injection is not possible due to the on-chip image reje ction. the if output is driv en by a source follower biased to create a driving impedance of 330 ? to interface with an off-chip 330 ? ceramic if filter. the voltage-conversion gain of the image-rejection mixer is approximately 18db at 315mhz and 15db at 433.92mhz with a 330 ? load. phase-locked loop (pll) the pt4301 utilizes a fixed divided-by-32 p ll to generate the receiver lo. the p ll consists of the voltage-controlled oscillator (vco), crystal oscillator, asynchronous 32 divider, charge pump, loop filter and phase-frequency detector (pfd). all these components are integr ated on-chip. the pfd compares two signals and produces an error signal which is proportional to the difference between the input phases. the error signal passes through a loop filter with an approximately 400khz bandwidth, and is used to contro l the vco which generates an lo frequency. the vco frequency is also fed through a frequency divider back to one input of the pfd, produci ng a feedback loop. thus, the output is locked to the reference frequency at the other input, which is derived from a crystal oscillator (i.e. f ref =( f rf ? f if )/32). the block diagram below show s the basic elements of the pll. figure 3. phase-locked loop in pt4301 to achieve an accurate frequency for the crystal oscillator, it is recommended to specify the suitable load capacitors, c14 and c15. specifying the value of 27pf is acceptable. choosing a lower value of crystal parallel equivalent capacitance, c 0 =1.5pf is also a suitable, but this may increase the price of the crystal itsel f. typically the value of c 0 _max is 7.0pf. figure 4. crystal oscillator circuit the reference oscillator frequency is clos e to 10.7 mhz intermediate frequency. it is necessary to avoid signal trace coupling between the reference oscillator and intermedi ate frequency. otherwise, it would degrade receiver performance. limiter/rssi the limiter is an ac coupled multi-stage amplifier with a cumulative gain of approxim ately 72db that possesses a band-pass characteristic. the -3db bandwidth of the limiter is around 12mhz. the limiter ci rcuit also produces an rssi voltage that is directly proportional to the input signal level with a slope of appr oximately 13mv/db. the rssi signal is used to demodulate ask-modulated receive signals in the s ubsequent baseband circuitry. the rssi output level has the dynamic range of approximately 80db. for:natertech
pt4301 v1.4 6 october 2010 automatic gain control (agc) the agc circuitry monitors the rssi voltage level. as descr ibed previously, when the rssi voltage reaches a first value corresponding to an rf input level of approximately -47dbm, the agc reduces the lna gai n by 20db, thereby reducing the rssi output by approximately 260mv. when the rssi voltage drops below a level corresponding to an rf input of approximately -63dbm, the agc sets the lna back to high-gain mode. figure 5 shows the change of rssi voltage versus rf input power. when the rssi leve l increases and then exceeds 1.77v (rf input power rising), the ag c switches the lna from high-gain m ode to low-gain mode. as rssi level decreases back to 1.16v (rf input power falling), the ag c switches the lna from low-gain mode back to high-gain mode. the agc has an additional protec tion mechanism (delay timer of 2 20 t ref seconds) when the lna is reset back to the high-gain state. rssi vs. rf input power 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 rf input power (dbm) rssi level (v) a gc dis able agc enable; rf pow er from l to h a gc enable; rf pow er f r om h to l figure 5. rssi vs. rf input power data filter the data filter is implemented as a 2nd-order low-pass sallen-ke y filter as shown in figure 6. the pole locations are set by the combination of two on-chip resist ors and two external capacitors. adjusti ng the value of the external capacitors changes the corner frequency to optimize for different data rates. the corner frequency should be set to approximately 1.5 times the highest expected dat a rate from the transmitter. figure 6. ideal sallen-key filter utilizing the on-board voltage follower and the two 100k ? on-chip resistors, a 2nd-order sallen-key low pass data filter may be constructed by adding 2 external capacitors bet ween pins 15 (dfo) and 18 (dffb) and to pin 17 (opp) as depicted in the page 2. the following tabl e shows the recommended values of the capacitors for different data rates. for:natertech
pt4301 v1.4 7 october 2010 data rate c11 (pf) c10 (pf) <2kb/s 1000 270 2kb/s - 10kb/s 470 100 10kb/s - 20kb/s 150 56 20kb/s - 40kb/s 56 15 >40kb/s n o t e 15 4.7 notes: 1. the maximum data rate of pt4301 is 50kb/s 2. the component values may be different, which depend upon the data duty and codec pattern. peak detector the peak detector generates a dc voltage which is proportional to the peak value of the received data signal. an external r-c network is necessary. the peak detector input is connected to the dat a filter internally, and its output is connected to pin 16 (dsn) through the r-c network. this out put may be used as an indicator of the received signal strength in wake-up circuits or used as a reference for data slicing. the time constant is calculated using the driving current of the op-amp in data filter, 100 a. figure 7. circuit for using peak detector for faster start-up data slicer the data slicer consists chiefl y of a fast comparator, which allows for a ma ximum receive data rate of up to 50kb/s. the maximum achievable data rate also depends upon the if filter bandwidth. both data s licer inputs are accessible off-chip to allow for easy adjustment of the slicing threshold. the output delivers a digital data signal (cmos level) for subsequent circuits. the self-adjusting threshold on pin 16 (dsn) is generated by an r-c network or peak detector, depending upon the baseband coding scheme. the suggested data slicer configuration is shown in figure 8. the cut-off frequenc y of the r-c integrator must be set lower than the lowest frequency appearing in the data si gnal to minimize distortion in the output signal. figure 8. circuit for generating data slicer threshold for:natertech
pt4301 v1.4 8 october 2010 demodulation with different circuit combinations, the pt4301 may ut ilize two demodulation modes, called ?peak mode? and ?average mode.? peak mode in conjunction with an external rc filt er (r3 and c13), the threshold voltage ma y be set at the peak detector output for comparison as shown in figure 7. the demodulated data enters into a quasi-mute st ate as the rf input signal becomes very small (when there is no rf signal received or the rf si gnal is too small) and the data output remains mostly at a logic ?high? level. if the environment is very noisy, t he r3 value may be enlarged to achieve better immunity against noise, but at the cost of less sensitivity. average mode when the ?average mode? has been set as shown in figure 8, the data output will exhibit a toggling behavior similar to random noise. in this mode, better s ensitivity may be achieved, but noise i mmunity is worse than in ?peak mode.? sensitivity and selectivity in digital radio systems, sensitivity is often defined as the lowest signal level at the receiver input that will achieve a specified bit error ratio (ber) at the output. the sensitiv ity of the pt4301 receiver, when used in the 434mhz application shown in figure 9, is typically -106dbm (ook modulated with 2kb/s, 50% duty cycle square wave in average mode) to achieve a 0.1% ber. the input was matched for a 50 ? signal source. at 315mhz, -108db m sensitivity is typically achievable. the selectivity is governed by the respons e of the receiver front-end circuitry, the channel filter (off-chip 10.7mhz if filter), and the data filter. note the if f ilter provides not only channel selectivity but also the interference rejection. wit hin the pass band of the receiver, no rejecti on for interfering signals is provided. sensitivity for 433.92 mhz frequency band -120 -100 -80 -60 -40 -20 0 411 414 417 420 423 426 429 432 435 rf input frequency (mhz) sensitivity (dbm) figure 9. sensitivity of pt4301 for:natertech
pt4301 v1.4 9 october 2010 power-down control the chip enable (ce) pin controls the power on/off behavior of the pt4301. connecting ce to ?high? sets the pt4301 to its normal operation mode; connecting ce to ?low? sets t he pt4301 to standby mode. the chip consumption current will be lower than 1 a in standby mode. once enabled, the pt4301 r equires <10ms to recover received data. figure 10. timing plot of pt4301 chip enable under 27c & -80dbm input power test condition. antenna design for a /4 dipole antenna and operating frequency, f (in mhz), the required antenna length, l (in cm), may be calculated by using the formula f l 7132 = for example, if the frequency is 315mhz, then the length of a /4 antenna is 22.6cm. if the calculated antenna length is too long for the application, then it may be reduced to /8, /16, etc. without degrading the input return loss. however, the rf input matching circuit may need to be re-optimized. note that in general, the shor ter the antenna, the worse the receiver sensitivity and the shorter the detection distance. usually, when designing a /4 dipole antenna, it is better to use a single conductive wire (diameter about 0.8mm to 1.6mm) rather than a multiple core wire. if the antenna is printed on the pcb, ensure there is neither any component nor ground plane underneath the antenna on the backside of pcb. for an fr4 pcb ( r =4.7) and a strip-width of 30m il, the length of the antenna, l (in cm), is calculated by r f c l = 4 where ? c ? is the speed of light (3 x10 10 cm/s) for:natertech
pt4301 v1.4 10 october 2010 antenna part esd protection pt4301 ic provides the esd level (human body mode) be tter than 3kv at lnain pin. however, the higher esd protection level would be required in system level for some applications. the extra esd prot ection level could rely on the external components. changing l1 from smd type to coil type could enhance esd protection level of around 1kv, and adding a shunt coil inductor l3 in the front of c4 to gain more esd protection enhancements. figure 11. antenna esd protection inductor of pt4301 pcb layout consideration proper pcb layout is extremely critical in achieving good rf performance. at t he very least, using a two-layer pcb is strongly recommended, so that one layer may incorporate a continuous ground plane. a large number of via holes should connect the ground plane areas between the top and bottom la yers. note that if the pcb design incorporates a printed loop antenna, there shoul d be no ground plane beneath the antenna. within the pt4301, the power supply rails of the lna and ot hers blocks should be separated fo r improving the isolation and minimizing the noise coupling effects. careful consideration must also be paid to the supply power and ground at the board level. the larger ground area plane should be placed as close as possible to all the vss pins. to reduce supply bus noise coupling, the power supply tr ace should be incorporate series-r, shunt -c filtering as shown in figure 12. figure 12. noise rejection filter for power bus c4 l1 l3 to lnain rf frequency f rf suggestion value of l3 315mhz 39nh 340mhz 39nh 390mhz 33nh 433.92mhz 27nh for:natertech
pt4301 v1.4 11 october 2010 absolute maximum ratings (v ss =0v) parameter symbol rating unit supply voltage range v dd5 v ss -0.3 to v ss +6.0 v operating temperature range topr -40 to +85 storage temperature range tstg -55 to +125 soldering temperature t sld 255 soldering time t sld 10 s recommended operating conditions (v ss =0v) parameter symbol value unit min. typ. max. supply voltage range v dd5 2.4 5.0 5.5 v operating temperature t a -40 27 85 for:natertech
pt4301 v1.4 12 october 2010 electrical characteristics (unless otherwise specified, v dd5 =5.0v, v ss =0v, ce=?high?, temp=27 ) parameter symbol condition value unit min. typ. max. general characteristics frequency range f rf 250 500 mhz maximum receiver input level p rf , max -25 -20 dbm sensitivity note1 s in ask note2 , peak power level @315mhz -114 -112 dbm ook, peak power level @315mhz -108 -106 dbm ask, peak power level @434mhz -112 -110 dbm ook, peak power level @434mhz -106 -104 dbm data rate note3 d rate 2 50 kb/s image rejection ratio imr 25 35 db lo leakage l lo measured at rf input -80 dbm system start-up time t start-up rf input power=-60dbm temp=27 10 ms power supply supply voltage v dd5 connect the supply voltage to vdd5 pin only 2.4 5.0 5.5 v consumption dc current i dd5 ce=?high?@315mhz 5.0 5.5 ma ce=?high?@434mhz 5.3 5.9 ma standby dc current i stand-b y ce=?low? 1.0 a lna power gain g lna matched to 50 ? @315mhz 13 16 20 db matched to 50 ? ? @434mhz 12 15 18 db noise figure nf lna matched to 50 ? 3 3.6 db input third-order intermodulation intercept point iip3 lna matched to 50 ? -20 dbm auto gain control (agc) note4 agc hysteresis h agc 16 db lna voltage gain reduction g red 20 30 db agc delay time dy agc t ref =1/f ref 2 20 t ref s down-conversion mixer conversion voltage gain g mix @315mhz 15 18 22 db @434mhz 12 15 18 db input third-order intermodulation intercept point iip3 mix -18 dbm output impedance z out , mix 330 ? pll reference frequency f ref 6 16 mhz vco frequency range f vco 220 550 mhz limiter amplifier and rssi if frequency f if 10.7 mhz input impedance z in , lim 330 ? rssi dynamic range dr rssi 80 db rssi gain sl rssi 13 mv/db notes: 1. ber=1 e-3 , data rate=2kb/s. 2. am 99% square-wave modulation. 3. the selection of data rate depends upon the component val ues use for the data filter, peak detector, and slicer. 4. agc hysteresis and lna gain reduction depend upon the gain setting and matching circuits of the lna. the agc delay time depe nds upon the pll reference frequency. for:natertech
pt4301 v1.4 13 october 2010 test board layout figure 12. example of test board layout for:natertech
pt4301 v1.4 14 october 2010 package information 24 pins, ssop, 150mil symbol min. nom. max. a - - 1.75 a1 0.10 - 0.25 b 0.20 - 0.30 c 0.10 - 0.25 d 8.66 bsc e 5.99 bsc e1 3.91 bsc e 0.635 bsc l 0.41 - 1.27 0 - 8 notes: 1. refer to jedec mo-137ae. 2. all dimensions are in millimeter. for:natertech
pt4301 v1.4 15 october 2010 important notice princeton technology corporation (ptc ) reserves the right to make co rrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product wit hout notice at any time. ptc cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ptc product. no circuit patent licenses are implied. princeton technology corp. 2f, 233-1, baociao road, sindian, taipei 23145, taiwan tel: 886-2-66296288 fax: 886-2-29174598 http://www.princeton.com.tw for:natertech

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